1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a transistor device on a bulk semiconductor substrate and the resulting substrate structures and transistor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If the voltage applied to the gate electrode is less than the threshold voltage (Vt) of the device, then there is no current flow through the device (ignoring undesirable leakage currents, which are hopefully relatively small). However, when the voltage applied to the gate electrode equals or exceeds the threshold voltage (Vt) of the device, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. During the fabrication of complex integrated circuit products using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors (NFET) and/or P-channel transistors (PFET), are formed on a substrate including a crystalline semiconductor layer.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure, etc.
One particular technique that has been employed in an effort to reduce or eliminate short channel effects has been to form the transistor devices on so-called silicon-on-insulator (SOI) substrates. In general, an SOI substrate is comprised of a bulk semiconducting substrate, a thin so-called active layer comprised of a semiconducting material positioned above the bulk substrate and a buried insulation layer (“BOX” layer) positioned between the bulk substrate and the active layer. Semiconductor devices, such as transistors, are formed in the active layer of an SOI substrate. As compared to transistor devices that are formed in a bulk semiconductor substrate, transistors formed in an active layer of an SOI substrate are fully insulated, due to the presence of the BOX layer. This structure improves device performance and can reduce some undesirable short channel effects. While transistor devices manufactured on SOI substrates may exhibit improved performance characteristics, SOI substrates are significantly more expensive than bulk semiconductor substrates, thereby increasing the cost of manufacturing integrated circuit products using SOI substrates. What is needed is a way to manufacture transistor devices on lower-cost bulk semiconductor substrates, wherein the transistor devices exhibit acceptable electrical performance characteristics and the manufacturing techniques used to make the transistor devices are compatible with existing processing tools and techniques.
The present disclosure is directed to various methods of forming transistor devices on a bulk semiconductor substrate and the resulting substrate structures and transistor devices.